Technology scaling has caused an enormous increase in timing variations, making it difficult to predict the cycle time of microprocessors. The cycle time is determined by the target performance with an added timing margin, necessary for an acceptable yield. The sensitivity of cycle time to variations is a major bottleneck in achieving the maximum performance and for meeting power specifications of applications with energy constraints.
The variations are classified into two categories; static variations like process variation and dynamic variations.
The examples of dynamic variations are supply voltage variations, temperature variations, radiation effects like single event upset (SEU) errors and ageing effect such as Negative Bias Temperature Instability (NBTI). The dynamic variations can also be workload dependent. For example, abrupt changes in the switching patterns can cause large transients current in the power mesh system and results in VDD drop on certain die locations.
The traditional worst case corner analysis based methodology for the determination of cycle time is overly pessimistic. In this approach, the impact of variations is compensated by the addition of an individual safety margin for each source of variability on the top of the nominal case requirements. For example, a traditional approach utilizes worst case supply voltage and frequency to overcome the impact of variations. Therefore, the added design margin represents an overly pessimistic very high total safety margin, which in turn results in chips failing the power specification.
The resultant die area with the traditional worst case design approach increases and also its capability to deal with dynamic variations is limited.
Post silicon tuning methods like VDD supply and body biasing are used to deal with static process variations. However, the effectiveness of these techniques is limited to deal with dynamic variations. A control signal based feedback loop mechanism, for tracking the operating conditions and then adaptively adjusting the supply voltage or body bias voltage, is a superior technique compared to the pessimistic worst-case corner based methodology. Another advantage with the adaptive VDD control mechanism is the ability to compensate for the delay degradation caused by the aging effects like electro migration and NBTI.
This pessimism built into the conventional approach can be reduced by designing the circuit with timing closure at the nominal corner and then always operating at the edge of failure by using error detection sequential logic.
Error detection sequential (EDS) circuits are utilized for preventing the errors (as is the case for “Canary flip flops” discussed below) or resorting to replaying the operation with an enhanced operating margin on the detection of timing errors (as is the case for “Razor flip flops” discussed below). However, the usage of existing EDS circuits requires a feedback mechanism for tuning the supply lines or body bias voltages in case of Canary FFs and pipeline flushing, architecture replay or cycle stalling for Razor FFs.
This complicates the design effort, thereby making it less attractive for the low cost system on chip applications.
Canary flip flops have a self-adjusting control mechanism. The detection of a warning signal adjusts the canary flip flop setting such as supply voltage or body bias voltage for the next clock cycles. The canary flip flop technique can only predict the occurrence of timing errors but cannot guarantee the complete elimination. The tuneable delay lines (setting the value of delay depending on the operating condition) used in Canary flips flops rely on an energy-intensive feedback mechanism. The ability to deal with an abrupt workload dependent fluctuation is also limited these FFs.
The razor flip flop mechanism, contrary to the Canary flip flop, detects and corrects the timing errors in the combinational path. The Razor FF computes an error signal by comparison of the sampled outputs of two flip flops. It is based on the assumption that the second flip flop is infallible and more robust compared to the first flip flop. The varying degree and nature of impact of VT mismatches, soft event upsets (SEU) error and ageing effects like NBTI on these two flip flops make this assumption precarious.
Razor FFs require the timing window just after the rising clock edge in order to detect a late arriving signal and flag it as a timing error. Then it resorts to re-execution mechanism or pipeline flushing to correct timing errors. The re-execution is performed through architecture replay. In this way, existing Razor FFs first detect the error and then in next cycle the errors are resolved by relying on architecture replay in next cycles or clock stalling for the consecutive FFS, as the case with the bubble razor.
This approach is more suitable for high-performance processors to support branch prediction. The timing errors are dealt with in a similar manner, such as by speculative execution. The timing error can be corrected by flushing the processing pipeline stages and reexecution from the last check point. However, this is impractical for general sequential circuits, real time processors for energy limited applications. The re-execution of instruction or architecture replay not only increases the power consumption but also impacts the processing throughput by increasing the instruction per cycle count. This results in fluctuation of computational latency that can be difficult to tolerate in many real time signal processing applications.
There remains a need for an error correction sequential element for critical combinational paths which can detect and correct timing errors without resorting to expensive feedback control mechanism as required by Canary flip flops or increased cycles per instruction count as used by Razor flip flops.